Nanotopography (NT) refers generally to features of a semiconductor wafers that exist on the nanoscopic scale, having a height of a few nanometers. NT includes topographic features attributable to the middle spatial-frequency components of wafer topography, and is defined as including spatial wavelengths of approximately 0.2-20 mm. Shorter wavelengths, higher spatial frequencies, are associated with micro-roughness, which is typically measured in a microscopic field-of-view. Longer wavelengths, lower spatial frequencies, are associated with wafer global topography such as global flatness (i.e., wafer thickness) and shape (i.e., free-form surface figure). Flatness, shape and NT are typically measured concurrently using a single data acquisition from a wafer.
NT metrology is often applied to the wafer front or back surface topographic data. This paradigm was established when wafer surface NT was an impediment to post-CMP film thickness uniformity during shallow trench isolation (STI) process integration. With the advent of 300 mm diameter wafers came double-side polished wafers where the NT was greatly reduced and no longer impacted STI process integration. NT metrology continued to be used as it appeared to scale with lithographic process needs. Recently, NT-to-lithography scaling appears to have stopped. Some wafer manufacturers believe that the wafer shape now dominates the NT signal using the surface topography paradigm. Existing wafer NT quality metrics may be improved by subtle improvements to the wafer shape. Yet the topography of interest in lithography is not shape, it is thickness.
Changes to the NT metrology and analysis paradigm may be desirable to achieve NT quality metrics that track with lithography. In particular, there is a desire to use NT metrology (NTM) for identification of wafer features impacting lithography (litho-NTM), for example, in manufacturing integrated circuits, especially during the era of multi-patterning. Wafer end users (e.g., lithographers, IC manufacturers) are seeking litho-NTM that better enables leading edge lithography, therefore high-volume wafer manufacturers are seeking litho-NTM to perform quality control that ensures wafers being used for lithography are of suitably high quality. Of particular interest are NT features on the high-volume manufacturing (HVM) wafers that impact lithography, because they are not possible to be adequately leveled. These features may be located on the front, back, or both surfaces of the wafer.
Modern step-and-scan lithography is designed to image very small-scale patterns on a wafer to produce an IC. The smaller scale can reduce the cost of circuits while making them faster and/or reducing their power consumption. Current advanced lithography systems, accordingly, require incredibly high precision and accuracy to achieve proper focus of the critical dimensions and enable overlay of the sequential lithography steps that make up the IC (transistors and interconnect). The wavelength of the light and the optical properties of the lithography lens have a great impact on the accuracy and precision at such small scales. Most current lithography systems utilize ultraviolet light with a wavelength of about 193 nm (0.2 μm). Extreme ultraviolet (EUV) lithography may be used for some lithographic exposure steps in HVM IC production using a wavelength of about 13.5 nm. “Step-and-scan” lithography refers to the pattern exposure path the lithography system takes across the wafer. The pattern on the reticle is printed at each site on the wafer by the lithography tool stepping to each site in sequence. At each site the reticle is scanned using an exposure slit while the lithography tool simultaneously translates and levels the wafer to pattern the photoresist (PR) deposited on the wafer.
After the wafer with deposited PR enters the lithography section of the exposure tool, it is chucked to an extremely flat surface known as a “litho chuck.” Wafer leveling to the projected image is based on chucked-wafer topography data. Each wafer is fixed to a chuck, typically using a back-side vacuum with a sealing ring around the back wafer perimeter (e.g., 0 atm at the back surface of a wafer and 1 atm at the front surface of a wafer), which eliminates or reduces many high-order (e.g., mm-level and cm-level) surface irregularities and variations in the wafer (commonly known as wafer shape). Electro-static chucking is required for EUV lithography where the ambient environment during exposure is already vacuum. The chucked-wafer front surface topography is therefore given by the sum of the three terms: the chuck topography, the wafer thickness, and the chuck-to-wafer gap. As an equation: Z(x,y)=Zchuck(x,y)+twafer(x,y)+gap (x,y); where the gap term is typically assumed to be approximately zero and may be negative when the wafer back surface comes below the ideal continuous surface of the chuck.
Modern lithography tools have more than one chuck so that the chucked-wafer topography can be measured at a metrology station within the exposure tool then translated over to an exposure station within the same tool while never being de-chucked between measurement and exposure. This approach permits improved designs for the metrology station than were not possible when using the exposure station, as in previous generation lithography tools when the chucked-wafer topography was measured during the exposure step. Having more than one chuck to transfer between stations enables the improved metrology to occur without reduction of the overall throughput. While the previously measured wafer is being exposed on its chuck, a new wafer is being measured on its chuck so the throughput remains exposure-time limited.
Existing NTM as it relates to wafer HVM was designed for quality control of wafer front-surface topography that might lead to film thickness variation after chemical mechanical polishing (CMP), particularly for shallow trench isolation (STI). This NTM development was largely driven by STI process difficulties with 200 mm wafers that were single-side polished (SSP). The CMP process tool applied pressure during front surface polishing that was largely independent of back surface topography (nano-scale or otherwise). For IC HVM, the use of stiff-pad polishing was preferred. However, front-surface NT then impacted post-CMP film thickness variation, mostly due to the SSP wafering process.
Currently, a double-side polished (DSP) wafer is typically used during leading edge IC HVM, and the issue of post-STI CMP film thickness variation is largely resolved by using the DSP wafer. However, the NTM developed for post-STI CMP analysis remained useful for the purpose of quality control for lithography. Over many years, the IC device design rules have continued to shrink while the existing NT metrics have proven difficult to scale accordingly.
At least some known litho-NTM processes are extensions of existing NTM philosophies, as previously applied to post-STI CMP analysis. In at least some cases, wafer surface data is filtered using convolution-based Gaussian, double-Gaussian, or other filters with small area convolution kernel functions made possible by using small spatial cut-off wavelengths (such as 5 mm rather than 20 mm or longer). Such filtering is not appropriate in the context of modern lithography for two primary reasons. First, the surface height data used includes the wafer surface figure or shape, which is almost entirely removed by chucking the wafer to one of the lithography tool's chucks. Second, the short cut-off wavelength of the circularly symmetric filter is not appropriate for the leveling under the slit exposure imaging area of the lithography tool. The resulting surface maps have little relevance to lithography.
Using surface data necessarily requires accounting for free-form wafer shape. When surface data is filtered (to remove higher-order topography, such as on the micrometer scale), a filter cutoff wavelength of 5 mm may be used to filter out the wafer shape data, which can introduce large artifacts around the fixed quality area (FQA; the area to receive the lithography where the wafer's specifications apply). Moreover, there is little value in filtering front and back surface data individually. In particular, analyzing the back surface alone ignores back surface interaction with the lithography chuck. The wafer front surface height during exposure is directly related to wafer thickness and not to the wafer's front and back surface topography.
In at least some known NTM processes, surface data analysis and reporting is performed using arbitrary “sites” or physical areas of a wafer surface. However, the reporting of NTM site metrics causes too much data to be reported with little benefit, and as such is not very useful for HVM wafer analysis. NTM site metrics, especially those reported for both front and back surfaces independently, will rarely contain data points of interest, and due to the volume of data reported, makes the resulting wafer HVM data difficult to mine for process signatures or quality decay.
This Background section is intended to introduce the reader to various aspects of art that may be related to various aspects of the present disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.